Microprocessors perform computational operations in a wide variety of applications. A processor may serve as a central or main processing unit in a stationary computing system such as a server or desktop computer. High execution speed is generally desirable for such desktop processors. In addition, processors are increasingly deployed in mobile computers such as laptops and Personal Digital Assistants (PDAs), and in embedded applications such as mobile phones, Global Positioning System (GPS) receivers, portable email clients, and the like. In such mobile applications, in addition to high execution speed, low power consumption and small size are commonly considered to be desirable.
Commonly computer programs are written as if the computer executing them had a very large (ideally, unlimited) amount of fast memory. Common modern processors simulate that ideal condition by employing a hierarchy of memory types, each having different speed and cost characteristics. The memory types in the hierarchy vary from very fast and very expensive at the top, to progressively slower but more economical storage types in lower levels. A common processor memory hierarchy may comprise registers (gates) in the processor at the top level; backed by one or more on-chip caches (SRAM); possibly an off-chip cache (SRAM); main memory (DRAM); disk storage (magnetic media with electro-mechanical access); and tape or CD (magnetic or optical media) at the lowest level. Common portable electronic devices have limited, if any, disk storage, and hence main memory, often limited in size, is the lowest level in the memory hierarchy.
High-speed, on-chip registers comprise the top level of a processor memory hierarchy. Discrete registers and/or latches are used as storage elements in the instruction execution pipeline. Common RISC instruction set architectures include a set of General Purpose Registers (GPRs) for use by the processor to store a wide variety of data, such as instruction op codes, addresses or address offsets, operands for and the intermediate and final results of arithmetic and logical operations, and the like.
In some processors, the logical GPRs directly correspond to physical storage elements. In other processors, register renaming, or dynamically assigning each logical GPR identifier to one of a large set of storage locations, or physical registers is employed. In either case, the storage elements accessed by logical GPR identifiers may be implemented either as discrete registers or as storage locations (or independently addressable subunits of storage locations) within a memory array.
Testing is an important part of IC manufacture. Testing memory arrays is particularly problematic. Automatic Test Pattern Generation (ATPG) methodology commonly used to test random logic comprises scanning an excitation pattern into one set of scan-chained registers or latches, applying the pattern to exercise random logic, capturing the results in another set of scan-chained registers or latches, and scanning the captured results out for comparison to expected values. Memory arrays cannot be efficiently tested using ATPG techniques since data does not flow through memory for subsequent capture and comparison, but rather is stored and retrieved.
Some processors test memory arrays by functional testing, wherein code is executed in the processor pipeline to write test patterns to the array (e.g., to logical GPRs), then read the values and compare to expected values. Functional testing is time consuming and inefficient because the processor must be initialized and test code loaded into the cache prior to executing the tests. Additionally, the control and observation point—within the pipeline—is far removed from the memory locations being tested, and it may be difficult to isolate uncovered faults from intervening circuits.
Accordingly, some processors with embedded memory arrays include a Built-In Self-Test (BIST) circuit that exercises the memory array during a test mode. A conventional BIST controller writes data patterns to the memory array, reads the data patterns, and compares the read data to expected data. In functional mode, the BIST controller is inactive and the memory array is controlled by the processor control circuits. In some BIST systems, I/O circuits surrounding the memory array, such as data steering logic that aligns data written to and read from the array to architecturally-defined bus alignment positions, are not tested.